Advanced Heterogeneous Programming on FPGAs with OmpSs@FPGA

Training details

Location

Barcelona, Spain (In person)

Start Date

18/03/2026

Time

10 : 00

End Date

18/03/2026

Target Audiance

Scientist

Teaching language(s)

English

Organizing institution

BSC

Delivery mode

On-site

Level

Intermediate

Format

Hands-on session, Lecture

Capacity or seats limit

Topics / Keywords

heterogenous programming, FPGA, tools

This tutorial will introduce the audience to the BSC tools for heterogenous programming on FPGA devices.

What You Will Learn

The students who finish this course will be able to develop benchmarks and simple applications with the OmpSs@FPGA programming model to be executed in FPGA boards, like Zedboard or Xilinx ZCU102.

Agenda

Morning: 10h-13h

10:00h – Heterogeneous Task-based parallel programming on FPGAs

OmpSs2 Task-Based Programming model
OmpSs2@FPGA Task-Based Programming model
Internals
Compilation and usage
Environment

10.40h – HLS highlights

Vivado/Vitis HLS basic directives

11:00h -Coffee break
11:30h – Case of Study: Step-by-Step Optimization: Matrix Multiply
13:00h – Lunch Break

Afternoon / 2:00pm – 4:00 pm

14.00h – Hands-on with document guide:

Matrix multiply/Any application of attendees on Zedboard (same case as step-by-step) –
Online connection to a cluster of FPGAs (zedboards)

16:00h – Adjourn

Instructor name(s)

Course Convener: Xavier Martorell, CS/Programming Models

Instructor's biography

BSC – Computer Sciences department

Daniel Jimenez-Gonzalez – Programming Models – Associate Researcher

Carlos Alvarez – Programming Models – Associate Researcher

Xavier Martorell – Programming Models – Parallel programming model – Group Manager

Course Description

It describes OmpSs@FPGA, as a productive programming environment for compute systems with FPGAs.

More specifically, the tutorial will:

Introduce the OmpSs@FPGA programming model, how to write, compile and execute applications on FPGAs
Show the “implements” feature to explot parallelism across cores and IP cores
Demonstrate how to analyze applications to determine which portions can be executed on FPGAs, and use OmpSs@FPGA to parallelize/optimize them.

Prerequisites

Good knowledge of C/C++
Basic knowledge of acceleration architectures and offloading models
Basic knowledge of Paraver/Extrae

Certificate/badge details

Certificate of Achievement